Patent · US Active

FPGA having a direct routing structure

US7961004B2 · kind B2 · utility

0Cited by

6References

21Claims

0Family size

Assignee

Sicronic Remote KG, LLC · US

Inventors

Deboleena Minz · New Delhi, IN
Kailash Digari · Noida, IN

Key dates

Filing date	Dec 22, 2009
Grant date	Jun 14, 2011
Priority date	—
Expiry date	Dec 22, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/17732
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A FPGA comprising, a direct interconnect structure for providing selective data routing without stressing the general-purpose routing resources and enabling high rate of data exchange within the FPGA. At least two IP cores are connected to each other through said direct interconnect structure for enabling simultaneous data interaction among the ports of said IP cores and for providing configurable bus width routing between said IP cores, and a plurality of logic blocks connected to said IP cores through said direct interconnect structure for enabling simultaneous data routing among said IP cores and said plurality of logic blocks.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.