Low leakage high performance static random access memory cell using dual-technology transistors
US7961499B2 · kind B2 · utility
3Cited by
1References
19Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 22, 2009 |
| Grant date | Jun 14, 2011 |
| Priority date | — |
| Expiry date | Jul 4, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell includes a storage element, a write circuit coupled to the storage element and a read circuit coupled to the storage element. At least a portion of the storage element and at least a portion of the write circuit are fabricated using a thicker functional gate oxide and at least a portion of the read circuit is fabricated using a thinner functional gate oxide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.