Design structure for compensating for variances of a buried resistor in an integrated circuit
US7962322B2 · kind B2 · utility
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8Claims
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Key dates
| Filing date | Jun 9, 2008 |
| Grant date | Jun 14, 2011 |
| Priority date | — |
| Expiry date | Jul 18, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/04
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a circuit that compensates for variances in the resistance of the buried resistor during operation of the integrated circuit using a waveform that is representative of the thermal characteristics of the buried resistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.