Method and system for integrating SRAM and DRAM architecture in set associative cache

US7962695B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Marc R. Faucher · South Burlington, US
• Hillery C. Hunter · Chappaqua, US
• William Robert Reohr · Ridgefield, US
• Peter A. Sandon · South Burlington, US
• Vijayalakshmi Srinivasan · New York, US
• Arnold S. Tran · South Burlington, US

Key dates

• Filing date: Dec 4, 2007
• Grant date: Jun 14, 2011
• Expiry date: Apr 12, 2030

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F12/123
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method of integrating a hybrid architecture in a set associative cache having a first type of memory structure for one or more ways in each congruence class, and a second type of memory structure for the remaining ways of the congruence class, includes determining whether a memory access request results in a cache hit or a cache miss; in the event of a cache miss, determining whether LRU way of the first type memory structure is also the LRU way of the entire congruence class, and if not, then copying the contents of the LRU way of the first type memory structure into the LRU way of the entire congruence class, and filling the LRU way of the first type memory structure with a new cache line in the event of a cache miss; and updating LRU bits, depending upon the results of the memory access request.