Electronic design for integrated circuits based on process related variations

US7962867B2 · kind B2 · utility

Assignee

• Cadence Design Systems, Inc. · US

Inventors

• David White · San Jose, US
• Taber H. Smith · San Jose, US

Key dates

• Filing date: Jan 28, 2008
• Grant date: Jun 14, 2011
• Expiry date: Jul 25, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/3212
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An electronic design is generated for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit. The generating includes adjusting the electronic design based on predictions of topographical and topographical-related feature dimension variations by a pattern-dependent model. An RC extraction tool is used in conjunction with the generating and adjusting of the electronic design. The process includes a fabrication process that will impart topographical variation to the integrated circuit and a lithography or etch process. Placement attributes for elements of the integrated circuit are determined.