Patent · US Active

Port assignment in hierarchical designs by abstracting macro logic

US7962877B2 · kind B2 · utility

2Cited by
4References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateAug 5, 2008
Grant dateJun 14, 2011
Priority date
Expiry dateAug 4, 2029

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F2119/12
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A method to reduce the problem complexity maintains a relatively high quality port assignment by abstracting local connections in the macro when performing the port assignment. This is done for netlength, congestion as well as timing. The internal netlist of the macro is abstracted in such a way that the optimization of the external interconnect can be done in an efficient manner. Three levels of abstractions are described. A first level optimizes the top level interconnect, a second level optimizes the top level and macro interconnects, while a third level optimizes the top level timing.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.