Patent · US Active

Via structure to improve routing of wires within an integrated circuit

US7962881B2 · kind B2 · utility

1Cited by

14References

21Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Markus Buehler · Holzgerlingen, DE
Ankit Gangwar · Darsi, IN
Juergen Koehl · Holzgerlingen, DE
Arun Kumar Mishra · Noida, IN

Key dates

Filing date	Jul 29, 2008
Grant date	Jun 14, 2011
Priority date	—
Expiry date	May 25, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/392
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In consideration for the fact that a connection on the upper layers of an integrated circuit needs to access a lower layer to connect to, e.g., a transistor, at least one via on each layer is required below the top layer used by a connection for each pin. The vias (i.e., the connection structures between wiring planes within an integrated circuit) are arranged such that the number of wiring resources blocked on the lower layers is reduced. Various rules govern which vias are chosen. The main characteristic is to elect only a certain number of wiring channels appropriate for the vias on a single layer and then apply an optimization within the restricted elected wiring channels on that layer to select the most appropriate vias.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.