Power MOS transistor incorporating fixed charges that balance the charge in the drift region
US7964913B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 8, 2008 |
| Grant date | Jun 21, 2011 |
| Priority date | — |
| Expiry date | Jan 8, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor layer of the second conductivity type is characterized by a first thickness. The semiconductor device includes a set of trenches having a predetermined depth and extending into the semiconductor layer of the second conductivity type, thereby defining interfacial regions disposed between the semiconductor layer of the second conductivity type and each of the trenches. The trenches comprises a distal portion consisting essentially of a dielectric material disposed therein and a proximal portion comprising the dielectric material and a gate material disposed interior to the dielectric material in the proximal portion of the trench. The semiconductor device further includes a source region coupled to the semiconductor layer of the second conductivity type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.