Method for fabrication of a semiconductor device and structure
US7964916B2 · kind B2 · utility
28Cited by
18References
8Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 2, 2010 |
| Grant date | Jun 21, 2011 |
| Priority date | — |
| Expiry date | Jun 2, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/837
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.