High boosting-ratio/low-switching-delay level shifter
US7965123B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 6, 2010 |
| Grant date | Jun 21, 2011 |
| Priority date | — |
| Expiry date | Jul 6, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018521
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit receives an input signal characterized by a first pair of rail voltages and generates in response thereto an output signal characterized by a second pair of rail voltages. The circuit comprises first and second transistors coupled in series between a high reference voltage and a low reference voltage. The input signal drives a control lead of the second transistor. The logical inverse of the input signal drives a control lead of a third transistor, which couples a charge source to the control lead of the first transistor in response thereto in order to turn off the first transistor. The charge source can be either a voltage source or a charged capacitive node. Of importance, the third transistor does not have to overcome contention with other transistors to turn off said first transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.