Ferroelectric memory device
US7965536B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2009 |
| Grant date | Jun 21, 2011 |
| Priority date | — |
| Expiry date | Dec 11, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to an aspect of the present invention, there is provided a ferroelectric memory device including: a cell unit including: a first select transistor having a first source, a first drain, and a first gate, one of the first source and the first drain being connected to a bit line; and a memory cell unit having a plurality of first memory cells, each of the first memory cells including a first ferroelectric capacitor and a first memory transistor; and a ferroelectric memory fuse including: a second select transistor having a second source, a second drain, and a second gate connected to a second select line, one of the second source and the second drain being connected to one end of the bit line; and a memory fuse unit having a plurality of second memory cells, each of the second memory cells including a second ferroelectric capacitor and a second memory transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.