Non-volatile single-event upset tolerant latch circuit
US7965541B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 25, 2008 |
| Grant date | Jun 21, 2011 |
| Priority date | — |
| Expiry date | Feb 17, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C14/009
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile single-event upset (SEU) tolerant latch is disclosed. The non-volatile SEU tolerant latch includes a first and second inverters connected to each other in a cross-coupled manner. The gates of transistors within the first inverter are connected to the drains of transistors within the second inverter via a first feedback resistor. Similarly, the gates of transistors within the second inverter are connected to the drains of transistors within the first inverter via a second feedback resistor. The non-volatile SEU tolerant latch also includes a pair of chalcogenide memory elements connected to the inverters for storing information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.