Register pointer trap to prevent errors due to an invalid pointer value in a register
US7966480B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 20, 2004 |
| Grant date | Jun 21, 2011 |
| Priority date | — |
| Expiry date | Jun 28, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Trap flags and a pointer trap are associated with registers in a processor. Each trap flag indicates whether a corresponding register has been written with valid data. If not, the trap flag is set to indicate that the register corresponding to the trap flag contains invalid data. During instruction processing, the pointer trap receives control signals from instruction fetch/decode logic on the processor indicating an instruction being processed calls for a register to be used as a pointer. If the specified pointer register has its corresponding trap flag set, then the pointer trap indicates that a processing exception has occurred. The interrupt logic/exception processing logic then causes a trap interrupt service routine (ISR) to be executed in response to the exception. The ISR prevents errors from being introduced in the instruction processing due to invalid pointer values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.