Patent · US Active

Methods of manufacturing semiconductor memory devices

US7968407B2 · kind B2 · utility

0Cited by
6References
10Claims
0Family size

Assignee

Inventor

Key dates

Filing dateApr 1, 2010
Grant dateJun 28, 2011
Priority date
Expiry dateApr 1, 2030

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D30/69

Abstract

A method of manufacturing a semiconductor memory device, the method including forming a tunnel insulation layer on a substrate, forming a preliminary charge trapping layer on the tunnel insulation layer, forming an etch stop layer on the preliminary charge trapping layer, wherein a portion of the preliminary charge trapping layer is not covered by the etch stop layer, removing the exposed portion of the preliminary charge trapping layer to form a charge trapping layer having a uniform thickness, forming a dielectric layer on the charge trapping layer, and forming a gate electrode on the dielectric layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.