Manufacturing process of a vertical-conduction MISFET device with gate dielectric structure having differentiated thickness and vertical-conduction MISFET device thus manufacture

US7968412B2 · kind B2 · utility

Assignee

• STMicroelectronics SA

Inventors

• Orazio Battiato · Gravina di Catania, IT
• Domenico Repici · Rometta Marea, IT
• Fabrizio Marco Di Paola · Catania, IT
• Giuseppe Arena · Messina, IT
• Angelo Magri · Mascalucia, IT

Key dates

• Filing date: Mar 11, 2010
• Grant date: Jun 28, 2011
• Expiry date: Mar 11, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/152

Abstract

According to an embodiment of a method for manufacturing a MISFET device, in a semiconductor wafer, a semiconductor layer is formed, having a first type of conductivity and a first level of doping. A first body region and a second body region, having a second type of conductivity, opposite to the first type of conductivity, and an enriched region, extending between the first and second body regions are formed in the semiconductor layer. The enriched region has the first type of conductivity and a second level of doping, higher than the first level of doping. Moreover, a gate electrode is formed over the enriched region and over part of the first and second body regions, and a dielectric gate structure is formed between the gate electrode and the semiconductor layer, the dielectric gate structure having a larger thickness on the enriched region and a smaller thickness on the first and second body regions. To form the enriched region, a first conductive layer is made on the semiconductor layer, an enrichment opening is formed in the first conductive layer, and a dopant species is introduced into the semiconductor layer through the enrichment opening. Furthermore, the formation of the…