Semiconductor device and manufacturing method thereof
US7968448B2 · kind B2 · utility
Inventors
Key dates
| Filing date | May 15, 2009 |
| Grant date | Jun 28, 2011 |
| Priority date | — |
| Expiry date | Dec 18, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device and manufacturing method thereof are disclosed. The device comprises a semiconductor die, a passivation layer, a wiring redistribution layer (RDL), an Ni/Au layer, and a solder mask. The semiconductor die comprises a top metal exposed in an active surface thereof. The passivation layer overlies the active surface of the semiconductor die, and comprises a through passivation opening overlying the top metal. The wiring RDL, comprising an Al layer, overlies the passivation layer, and electrically connects to the top metal via the passivation opening. The solder mask overlies the passivation layer and the wiring RDL, exposing a terminal of the wiring RDL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.