Patent · US Active

Systems and methods for test time outlier detection and correction in integrated circuit testing

US7969174B2 · kind B2 · utility

9Cited by

25References

15Claims

0Family size

Assignee

OptimalTest Ltd. · IL

Inventors

Gil Balog · Jerusalem, IL
Reed Linde · Cameron Park, US
Avi Golan · Nes Ziona, IL

Key dates

Filing date	Apr 3, 2009
Grant date	Jun 28, 2011
Priority date	—
Expiry date	Dec 8, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/318511
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.