Multiple memory standard physical layer macro function
US7969799B2 · kind B2 · utility
4Cited by
1References
22Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 25, 2008 |
| Grant date | Jun 28, 2011 |
| Priority date | — |
| Expiry date | Sep 16, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory interface physical layer macro including one or more embedded input/output (I/O) buffers, one or more memory interface hardmacros and control logic. The one or more embedded input/output (I/O) buffers support a plurality of I/O supply voltage levels. The one or more memory interface hardmacros are coupled to the one or more embedded I/O buffers. The control logic controls the one or more hardmacros and the one or more I/O buffers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.