System and method for clock drift compensation
US7970086B2 · kind B2 · utility
1Cited by
5References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2007 |
| Grant date | Jun 28, 2011 |
| Priority date | — |
| Expiry date | Apr 20, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0041
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method for processing a signal includes monitoring an over-sampled signal to detect deviations in a number of fill samples, and providing an electronic delay adjustment to a signal path. If a deviation in the number of fill samples is detected, the electronic delay adjustment from the signal path is removed in one or more steps until all of the electronic delay adjustment is removed from the signal path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.