Apparatus and method for implementing speculative clock gating of digital logic circuits
US7971161B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2008 |
| Grant date | Jun 28, 2011 |
| Priority date | — |
| Expiry date | Jan 27, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for implementing speculative clock gating of digital logic circuits in a multiple stage pipeline design includes generating, in a first pipeline stage n, a valid control signal that is input to a first register in a second pipeline stage n+1, the valid control signal indicative of when an operation is qualified to be performed by the second pipeline stage n+1; and generating, in the first pipeline stage, a speculative valid control signal that is used to gate a clock signal to a plurality of additional registers in the second pipeline stage, wherein the speculative valid control signal is generated using only a subset of a total number of control inputs used in generating the valid control signal, and wherein the clock signal is sent directly, without gating, to the first register in the second pipeline stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.