Method and system for implementing cached parameterized cells
US7971175B2 · kind B2 · utility
22Cited by
11References
32Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 27, 2007 |
| Grant date | Jun 28, 2011 |
| Priority date | — |
| Expiry date | May 3, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Parameterized cells are cached and provided by the plug-in to increase the speed and efficiency of an application for circuit design. This allows source design to be read-interoperable and also enables some basic write-interoperability in the source design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.