Vertical PNP transistor and method of making same
US7972919B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2005 |
| Grant date | Jul 5, 2011 |
| Priority date | — |
| Expiry date | Dec 7, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/969
Abstract
The present invention relates to a device structure located in a semiconductor substrate and containing high performance vertical NPN and PNP transistors. Specifically, the vertical PNP transistor has an emitter region, and the vertical NPN transistor has an intrinsic base region. The emitter region of the vertical PNP transistor and the intrinsic base region of the vertical NPN transistor are located in a single silicon germanium-containing layer, and they both contain single crystal silicon germanium. The present invention also relates to a method for fabricating such a device structure based on collateral modification of conventional fabrication processes for CMOS and bipolar devices, with few or no additional processing steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.