Semiconductor memory device and a method of manufacturing the same, a method of manufacturing a vertical MISFET and a vertical MISFET, and a method of manufacturing a semiconductor device and a semiconductor device
US7972920B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 4, 2010 |
| Grant date | Jul 5, 2011 |
| Priority date | — |
| Expiry date | Mar 6, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
Abstract
Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.