TEG pattern for detecting void in device isolation layer and method of forming the same
US7973309B2 · kind B2 · utility
7Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 4, 2009 |
| Grant date | Jul 5, 2011 |
| Priority date | — |
| Expiry date | Oct 8, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a test element group (TEG) pattern for detecting a void in a device isolation layer. The TEG pattern includes active regions which are parallel to each other and extend in a first direction, a device isolation layer that separates the active regions, a first contact that is formed across the device isolation layer and a first one of the active regions that contacts a surface of the device isolation layer, and a second contact that is formed across the device isolation layer and a second one of the active regions that contacts another surface of the device isolation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.