Single transistor charge transfer random access memory
US7973348B1 · kind B1 · utility
Inventors
Key dates
| Filing date | Aug 4, 2005 |
| Grant date | Jul 5, 2011 |
| Priority date | — |
| Expiry date | Oct 2, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/223
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile semiconductor memory device is described where each memory cell is composed of a single field effect transistor with a dual gate dielectric comprising a dielectric interfacial layer in contact with a silicon substrate and a ferroelectric layer in between the interfacial layer and the gate electrode. To program (write) the cell the ferroelectric layer is polarized in one of two directions, the ferroelectric polarization creating a large electric field in the interfacial layer. This electric field causes electrons or holes to be transported across the interfacial layer and be trapped in the ferroelectric layer establishing a high (erased) or low (programmed) threshold voltage depending on the direction of the ferroelectric polarization representing the two logic states. To read the memory cell a voltage is applied to the drain of the selected transistor and depending on whether a high or low threshold state was programmed into the cell a low or high current is sensed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.