Method and apparatus for calibrating internal pulses in an integrated circuit
US7973549B2 · kind B2 · utility
11Cited by
11References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2007 |
| Grant date | Jul 5, 2011 |
| Priority date | — |
| Expiry date | Jan 3, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31726
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and circuit for measuring internal pulses includes an enable circuit configured to receive a control signal from an on-chip built-in tester to enable measurement of internal circuits. A delay chain is configured to receive a pulse signal from an on-chip circuit component. Sampling latches each include a data input coupled between adjacent delay elements of the delay chain and synchronized with the clock signal such that a transition in the pulse signal is indicated by comparing adjacent digital values in an output sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.