DDR memory controller
US7975164B2 · kind B2 · utility
23Cited by
6References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2008 |
| Grant date | Jul 5, 2011 |
| Priority date | — |
| Expiry date | Oct 28, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DDR memory controller is described wherein a core domain capture clock is created by programmably delaying the core clock of the memory controller. The delay of this capture clock is calibrated during a power on the initialization sequence in concert with a DDR memory in a system environment, thereby minimizing the effects of system delays and increasing both device and system yield. An additional embodiment also includes programmably delaying the incoming dqs signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.