Patent · US Active

On-chip scan clock generator for ASIC testing

US7975197B2 · kind B2 · utility

4Cited by

3References

16Claims

0Family size

Assignee

LSI · US

Inventors

Iain Clark · Rugby, GB
Juergen Dirks · Holzkirchen, DE

Key dates

Filing date	Mar 31, 2003
Grant date	Jul 5, 2011
Priority date	—
Expiry date	Jun 5, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/318552
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

A scan clock generator includes a clock signal input for receiving a clock signal, a scan shift mode signal input for receiving a scan shift mode signal, and a sequence controller coupled to the clock signal input for gating a selected number of clock signal pulses at a time to generate a sequence of nonconcurrent scan clock signals at separate outputs respectively in response to a first state of the scan shift mode signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.