Wafer-level flip-chip assembly methods
US7977155B2 · kind B2 · utility
0Cited by
15References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 4, 2007 |
| Grant date | Jul 12, 2011 |
| Priority date | — |
| Expiry date | Nov 1, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15787
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of packaging integrated circuit structures is provided. The method includes providing a wafer having bonding conductors on a surface of the wafer, and applying a compound underfill onto the surface of the wafer. The compound underfill includes an underfill material and a flux material. A die is then bonded on the wafer after the step of applying the compound underfill, wherein solder bumps on the die are joined with the bonding conductors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.