Method of forming a gate insulator in group III-V nitride semiconductor devices
US7977254B2 · kind B2 · utility
6Cited by
1References
10Claims
0Family size
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Key dates
| Filing date | Jun 27, 2007 |
| Grant date | Jul 12, 2011 |
| Priority date | — |
| Expiry date | May 11, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02258
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a gate insulator in the manufacture of a semiconductor device comprises conducting a photo-assisted electrochemical process to form a gate-insulating layer on a gallium nitride layer of the semiconductor device, wherein the gate-insulating layer includes gallium oxynitride and gallium oxide, and performing a rapid thermal annealing process. The photo-assisted electrochemical process uses an electrolyte bath including buffered CH3COOH at a pH between about 5.5 and 7.5. The rapid thermal annealing process is conducted in O2 environment at a temperature between about 500° C. and 800° C.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.