MOS transistor and semiconductor device

US7977709B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Marc Tiebout · Birkenfeld, DE
• Daniel Kehrer · Eferding, AT
• Domagoj Siprak · Munich, DE
• Pierre Mayr · Essen, DE
• Johannes Kunze · Mülheim, DE
• Christopher Weyers · Bochum, DE

Key dates

• Filing date: Jan 2, 2008
• Grant date: Jul 12, 2011
• Expiry date: Jun 24, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/30105
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

According to one embodiment of the present invention, a MOS transistor includes a semiconductor layer including a source region, a drain region, and a channel region disposed between the source region and the drain region. A gate structure is arranged above the channel regions. A source wiring structure is arranged above the source region and is connected to the source region. A drain wiring structure is arranged above the drain region and is connected to the drain region. The width of the source wiring structure is larger than the width of the drain wiring structure, and the height of the source wiring structure is smaller than the height of the drain wiring structure, or vice versa.