LDMOS devices with improved architectures
US7977715B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 17, 2008 |
| Grant date | Jul 12, 2011 |
| Priority date | — |
| Expiry date | Sep 17, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An LDMOS device includes a substrate of a first conductivity type, an epitaxial layer on the substrate, a buried well of a second conductivity type opposite to the first conductivity type in a lower portion of the epitaxial layer, the epitaxial layer being of the first conductivity type below the buried layer. The device further includes a field oxide located between a drain and both a gate on a gate oxide and a source with a saddle shaped vertical doping gradient of the second conductivity type in the epitaxial layer above the buried well such that the dopant concentration in the epitaxial layer above the buried well and below a central portion of the field oxide is lower than the dopant concentration at the edges of the field oxide nearest the drain and nearest the gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.