Semiconductor memory device and manufacturing method thereof

US7977738B2 · kind B2 · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Yoshihiro Minami · Tokyo, JP
• Takashi Ohsawa · Tokyo, JP
• Tomoaki Shino · Yokohama, JP
• Takeshi Hamamoto · Tokyo, JP
• Akihiro Nitayama · Kawasaki, JP

Key dates

• Filing date: Jul 2, 2009
• Grant date: Jul 12, 2011
• Expiry date: Nov 30, 2029

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2211/4016

Abstract

A semiconductor memory device includes bodies electrically floating; sources; drains; gate electrodes, each of which is adjacent to one side surface of the one of the bodies via a gate dielectric film; plates, each of which is adjacent to the other side surface of the one of the bodies via a plate dielectric film; first bit lines on the drains, the first bit lines including a semiconductor with a same conductivity type as that of the drains; and emitters on the semiconductor of the first bit lines, the emitters including a semiconductor with an opposite conductivity type to that of the semiconductor of the first bit lines, wherein the emitters are stacked above the bodies and the drains.