Fusion quad flat semiconductor package
US7977774B2 · kind B2 · utility
18Cited by
287References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 10, 2007 |
| Grant date | Jul 12, 2011 |
| Priority date | — |
| Expiry date | Mar 14, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package which includes a generally planar die paddle defining multiple peripheral edge segments and a plurality of leads which are segregated into at least two concentric rows. Connected to the top surface of the die paddle is at least one semiconductor die which is electrically connected to at least some of the leads of each row. At least portions of the die paddle, the leads, and the semiconductor die are encapsulated by a package body, the bottom surfaces of the die paddle and the leads of at least one row thereof being exposed in a common exterior surface of the package body.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.