Bump with multiple vias for semiconductor package and fabrication method thereof, and semiconductor package utilizing the same
US7977789B2 · kind B2 · utility
54Cited by
3References
19Claims
0Family size
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Inventor
Key dates
| Filing date | Aug 28, 2006 |
| Grant date | Jul 12, 2011 |
| Priority date | — |
| Expiry date | Jul 10, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A bump for a semiconductor package forms a polymer layer having multiple vias on an electrode pad above a semiconductor chip to increase an electrical contact area between the electrode pad and a metal bump. Further, the bump forms a polymer layer having multiple vias on a redistribution electrode pad to increase a surface area of an electrode interconnection. The multiple vias increase electrical and mechanical contact areas, thereby preventing current crowding and improving joint reliability. The bump for a semiconductor package may further comprise a stress relaxation layer at the lower portion of the bump.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.