Semiconductor device having delay locked loop and method for driving the same
US7977986B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 18, 2009 |
| Grant date | Jul 12, 2011 |
| Priority date | — |
| Expiry date | Aug 18, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay locked loop includes: a control voltage generator configured to generate a voltage control signal having a voltage level corresponding to a phase difference between an external clock and a feedback clock; a voltage controlled delay line configured to generate a plurality of output signals by reflecting a different delay time on the external clock in response to the voltage control signal; an internal clock multiplexer configured to output one of the plurality of output signals as an internal clock in response to a skew information signal; a delay replica model configured to output the feedback clock by reflecting a delay of an actual clock/data path on the internal clock; and a skew information signal generator configured to generate the skew information signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.