Microprocessor with selective substrate biasing for clock-gated functional blocks
US7978001B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2008 |
| Grant date | Jul 12, 2011 |
| Priority date | — |
| Expiry date | Apr 24, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A microprocessor according to one embodiment includes a supply node providing a core voltage, a functional block, a charge node, select logic, and substrate bias logic. The functional block has multiple power modes and includes one or more semiconductor devices and a substrate bias rail routed within the functional block and coupled to a substrate connection of at least one semiconductor device. The select logic couples the substrate bias rail to the charge node when the functional block is in a low power mode and clamps the substrate bias rail to the supply node when the functional block is in a full power mode. The substrate bias logic charges the charge node to a bias voltage at an offset voltage relative to the core voltage when the functional block is in the low power mode. Semiconductor devices may be provided to clamp or otherwise couple the bias rail.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.