Test mode circuitry for a programmable tamper detection circuit
US7978095B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2006 |
| Grant date | Jul 12, 2011 |
| Priority date | — |
| Expiry date | Mar 23, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes an output pad, an alarm output pad, and a test mode output pad. A first multi-bit register is programmable to store programmable data such as data that identifies a customer for whom the integrated circuit has been manufactured. A second multi-bit register is programmable to store customer specified threshold data. A first circuit selectively couples the first and second multi-bit registers to the output pad. The first circuit is operable responsive to the integrated circuit being placed into a test mode to perform parallel-to-serial conversion of either the customer identification data stored in the first multi-bit register or the customer specified threshold data stored in the second multi-bit register and drive the converted data for output through the output pad. The integrated circuit further includes a tamper detection circuit operable responsive to the customer specified threshold data to generate a tamper alarm signal. A second circuit selectively couples the tamper alarm signal to the alarm output pad and test mode output pad depending on whether the integrated circuit is in a test mode. More specifically, the second circuit operates to drive…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.