Semiconductor memory devices having vertically-stacked transistors therein
US7978561B2 · kind B2 · utility
3Cited by
25References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2009 |
| Grant date | Jul 12, 2011 |
| Priority date | — |
| Expiry date | Oct 15, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a semiconductor device having transistors of stacked structure. The semiconductor memory device having transistors includes a memory cell array block which includes a plurality of word lines and a plurality of memory cells which each includes at least one first transistor connected between the plurality of word lines, and a word line decoder which includes a plurality of drivers which drive the plurality of word lines, respectively, wherein a plurality of word lines are disposed on a first layer, and a plurality of drivers are disposed on at least two second layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.