Distributed test compression for integrated circuits
US7979764B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2007 |
| Grant date | Jul 12, 2011 |
| Priority date | — |
| Expiry date | May 15, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318547
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for testing integrated circuits is provided. The method provides for incorporating compression and decompression logic into each sub-component of an integrated circuit, developing test modes that target different sub-components of the integrated circuit, selecting one of the test modes, applying a test pattern to one or more sub-components of the integrated circuit targeted by the one test mode, comparing a response from application of the test pattern to a known good response, and diagnosing the response to determine which part of the one or more sub-components targeted by the one test mode failed when the response does not match the known good response.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.