MOS structures that exhibit lower contact resistance and methods for fabricating the same
US7981749B2 · kind B2 · utility
2Cited by
3References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 20, 2007 |
| Grant date | Jul 19, 2011 |
| Priority date | — |
| Expiry date | Oct 20, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
MOS structures that exhibit lower contact resistance and methods for fabricating such MOS structures are provided. In one method, a semiconductor substrate is provided and a gate stack is fabricated on the semiconductor substrate. An impurity-doped region within the semiconductor substrate aligned with the gate stack is formed. Adjacent contact fins extending from the impurity-doped region are fabricated and a metal silicide layer is formed on the contact fins. A contact to at least a portion of the metal silicide layer on at least one of the contact fins is fabricated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.