Self aligned ring electrodes
US7981755B2 · kind B2 · utility
4Cited by
3References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2007 |
| Grant date | Jul 19, 2011 |
| Priority date | — |
| Expiry date | Oct 25, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/884
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention in one embodiment provides a method of manufacturing an electrode that includes providing at least one metal stud positioned in a via extending into a first dielectric layer, wherein an electrically conductive liner is positioned between at least a sidewall of the via and the at least one metal stud; recessing an upper surface of the at least one metal stud below an upper surface of the first dielectric layer to provide at least one recessed metal stud; and forming a second dielectric atop the at least one recessed metal stud, wherein an upper surface of the electrically conductive liner is exposed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.