Common plate capacitor array connections, and processes of making same

US7981756B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Nick Lindert · Beaverton, US
• Brian S. Doyle · Portland, US
• Dinesh Somasekhar · Hillsboro, US
• Christopher J. Jezewski · Portland, US
• Swaminathan Sivakumar · Portland, US
• Kevin X. Zhang · Austin, US
• Stephen Wu · Portland, US

Key dates

• Filing date: Dec 22, 2008
• Grant date: Jul 19, 2011
• Expiry date: Jun 7, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/00

Abstract

A process of forming a semiconductive capacitor device for a memory circuit includes forming a first capacitor cell recess and a second capacitor cell recess that are spaced apart by a capacitor cell boundary of a first height. The process includes lowering the first height of the capacitor cell boundary to a second height. A common plate capacitor bridges between the first recess and the second recess over the boundary above the second height and below the first height.