Circuit with fuse/anti-fuse transistor with selectively damaged gate insulating layer
US7982245B2 · kind B2 · utility
7Cited by
6References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2008 |
| Grant date | Jul 19, 2011 |
| Priority date | — |
| Expiry date | Oct 21, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit is disclosed which includes a main transistor and at least one of a fuse transistor or an anti-fuse transistor (“fuse/anti-fuse transistor”). Each transistor type includes an active region formed in a semiconductor substrate, a gate stack comprising a gate insulation layer and a gate electrode sequentially formed on the active region, and source/drain regions separated across the gate stack, but the gate insulation layer of the fuse/anti-fuse transistor is selectively damaged during fabrication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.