Error-correction memory architecture for testing production errors
US7984358B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2009 |
| Grant date | Jul 19, 2011 |
| Priority date | — |
| Expiry date | Jun 8, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a first circuit generating error-correction (EC) bits based on test data. Memory comprises a plurality of memory lines each including a data portion storing the test data and an error-correction (EC) portion storing corresponding ones of the EC bits. An input receives the test data. A switching device selectively outputs one of the test data from the input and the EC bits and the test data from the first circuit to the memory. The test data comprise T pairs of test vectors. A first test vector of each of the T pairs of test vectors is an inverse of a second test vector of each of the T pairs of test vectors. Each of the first test vectors in the T pairs of test vectors is unique and each of the second test vectors in the T pairs of test vectors is unique. T is an integer greater than one.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.