Power network stacked via removal for congestion reduction
US7984397B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2009 |
| Grant date | Jul 19, 2011 |
| Priority date | — |
| Expiry date | Sep 25, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY04S40/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of automatically reducing stacked vias while minimizing voltage drop in a power network of an integrated circuit (IC) is provided. In this method, any feasible (i.e. other than connectivity-necessary and uncongested stacked vias) stacked vias of the power network can be virtually removed. If a target voltage drop of the power network is exceeded, then a measurement of the severity of at least a maximum voltage drop on the IC can be updated. After this updating, a set of voltage drop improvement stacked vias can be virtually returned to the power network. The steps of determining whether the target voltage drop is exceeded, updating the severity of the voltage drop at one or more hot spots, and virtually returning the set of additional stacked vias can be repeated until the target voltage drop is not exceeded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.