Hierarchy-based analytical placement method for an integrated circuit
US7984410B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2008 |
| Grant date | Jul 19, 2011 |
| Priority date | — |
| Expiry date | Aug 19, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A placer produces a global placement plan specifying positions of cell instances to be interconnected by nets within an integrated circuit (IC) by initially clusterizing cell instances to form a pyramidal hierarchy of blocks and generating an initial global placement plan specifying a position of each block at a highest level of the hierarchy. The placer then declusterizes the global placement plan by replacing the highest level blocks with their component blocks and then improves the routability of the global placement plan by iteratively moving specified block positions in directions and by distances dynamically determined by analyzing the global placement plan and an objective function having a total wirelength term and having a bin density term reflecting density of blocks in specified areas (bins) of the IC. The placer iteratively repeats the declusterization and routability improvement process until the global placement plan specifies positions of all blocks residing at the lowest level of the hierarchy, with weighting of the bin density term adjusted when necessary during each iteration of the routability improvement process to provide sufficient white space in each bin. The…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.