Method and apparatus for exploiting thread-level parallelism
US7984431B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2007 |
| Grant date | Jul 19, 2011 |
| Priority date | — |
| Expiry date | May 16, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/456
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one example embodiment, there is disclosed herein uses partial recurrence relaxation for parallelizing DOACROSS loops on multi-core computer architectures. By one example definition, a DOACROSS may be a loop that allows successive iterations executing by overlapping; that is, all iterations must impose a partial execution order. According to one embodiment, the inventive subject matter may be used to transform the dependence structure of a given loop with recurrences for maximal degree of thread-level parallelism (TLP), where the threads can be mapped on to either different logical processors (in a hyperthreaded processor) or can be mapped onto different physical cores (or processors) in a multi-core processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.