Method of forming collapse chip connection bumps on a semiconductor substrate
US7985622B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2008 |
| Grant date | Jul 26, 2011 |
| Priority date | — |
| Expiry date | Jan 1, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/054
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming collapse chip connection bumps on a semiconductor substrate is provided. The method includes providing a semiconductor substrate having a plurality of bump vias on a top surface of the semiconductor substrate and electroplating the plurality of bump vias to form a plurality of via pads on the top surface of the semiconductor substrate. The method also includes disposing a plurality of solder microballs on the top surface of the semiconductor substrate, wherein each solder microball is placed on a corresponding via pad on the semiconductor substrate and reflowing the plurality of solder microballs to form the collapse chip connection bumps on the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.