Structures and methods for improving solder bump connections in semiconductor devices
US7985671B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2008 |
| Grant date | Jul 26, 2011 |
| Priority date | — |
| Expiry date | Dec 29, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The method includes forming an upper wiring layer in a dielectric layer and depositing one or more dielectric layers on the upper wiring layer. The method further includes forming a plurality of discrete trenches in the one or more dielectric layers extending to the upper wiring layer. The method further includes depositing a ball limiting metallurgy or under bump metallurgy in the plurality of discrete trenches to form discrete metal islands in contact with the upper wring layer. A solder bump is formed in electrical connection to the plurality of the discrete metal islands.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.